Thermally enhanced package to reduce thermal interaction between dies

ABSTRACT

A method of reducing heat flow between IC chips and the resulting device are provided. Embodiments include attaching plural IC chips to an upper surface of a substrate; forming a lid over the IC chips; and forming a slit through the lid at a boundary between adjacent IC chips.

RELATED APPLICATIONS

The present application is a Divisional of application Ser. No.15/799,600, filed on Oct. 31, 2017, which is a Divisional of applicationSer. No. 15/205,496, filed on Jul. 8, 2016, now U.S. Pat. No. 9,859,262,which are incorporated herein by reference in their entirety.

TECHNICAL FIELD

The present disclosure relates to the manufacture of semiconductordevices, such as integrated circuits (ICs). The present disclosure isparticularly applicable to forming semiconductor packages with chipsmounted close to each other, particularly for the 14 nanometer (nm)technology node and beyond.

BACKGROUND

In a 2.5D package, multiple IC chips (e.g., a logic chip, a memorystack, etc.) are mounted close together to improve performance,bandwidth and/or functionality. Since multiple IC chips are close toeach other, they are thermally coupled together. If one of the IC chipsdissipates more power than the others, heat may flow from the high powerIC chip to a lower power IC chip. The IC fabrication technology for eachIC could be different, and hence the junction temperature specificationcan be different as well depending on technology, functionality,performance and bandwidth. The lower power IC could have a lowerjunction temperature specification. As a result, thermal management ofheat generated in the 2.5D package becomes challenging.

For example, FIG. 1 illustrates heat flow in a package due to thermalinteraction between IC chips. In FIG. 1, a substrate 101, with an uppersurface and a lower surface, has solder balls 103 metallurgically bondedto a solder ball receiving area on the lower surface of the substrate101. IC chips (e.g., a logic chip 105 and a memory stack 107) areattached to the upper surface of the substrate 101 by controlledcollapse chip connection (C4) balls 109 via an interposer 108. The logicchip 105 and the memory stack 107 are mounted on the interposer 108 withmicro-bumps 106. A lid 111 is formed over the logic chip 105 and thememory stack 107. The lid 111 is thermally connected to the logic chip105 and the memory stack 107 by a thermal interface material (TIM1) 113.The lid 111 also includes lid feet in mechanical contact with theperimeter of the upper surface of the substrate by an adhesive 115. Aheat sink 117 is formed over the lid 111. The heat sink 117 is thermallyconnected to the lid 111 by TIM2 119. Arrows 121 represent heat flowthrough the package. As illustrated, though the heat sink 117 includes aplurality of fins, heat generated within the package continues to flowbetween the logic chip 105 and the memory stack 107. As a result, thesemiconductor devices tend to overheat or fail because of insufficientheat transfer.

A need therefore exists for methodology enabling formation of asemiconductor packaged with reduced thermal interaction between the ICchips and the resulting device.

SUMMARY

An aspect of the present disclosure is forming a slit through asemiconductor package lid at a boundary between a logic chip and amemory stack.

Another aspect of the present disclosure is forming a semiconductorpackage with at least one vertical heat pipe in direct thermal contactwith an IC chip and a heat sink.

Another aspect of the present disclosure is a semiconductor package witha lid having a slit at a boundary between a logic chip and a memorystack.

Another aspect of the present disclosure is a semiconductor package withat least one vertical heat pipe in direct thermal contact with an ICchip and a heat sink.

Additional aspects and other features of the present disclosure will beset forth in the description which follows and in part will be apparentto those having ordinary skill in the art upon examination of thefollowing or may be learned from the practice of the present disclosure.The advantages of the present disclosure may be realized and obtained asparticularly pointed out in the appended claims.

According to the present disclosure, some technical effects may beachieved in part by a method including: attaching plural IC chips to anupper surface of a substrate; forming a lid over the IC chips; andforming a slit through the lid at a boundary between adjacent IC chips.

Aspects of the present disclosure include the IC chips including: alogic chip; and at least one memory stack adjacent the logic chip.Further aspects include a method for forming the slit by: punch and dieat a boundary between the logic chip and a memory stack. Other aspectsinclude forming a slit between the logic chip and each memory stack.Additional aspects include forming a heat sink over the lid; and formingat least one vertical heat pipe through the heat sink and the lid, downto the IC chips, wherein each vertical heat pipe is in direct thermalcontact with an IC chip and the heat sink.

Another aspect includes a method for forming the vertical heat pipes by:forming co-axial holes in the lid and the heat sink; and inserting thevertical heat pipes through the holes for direct thermal contact withthe IC and the heat sink. Further aspects include thermally connectingthe lid to the IC chips by a first thermal interface material (TIM1);and thermally connecting the heat sink to the lid by a second thermalinterface material (TIM2), wherein a length of the vertical heat pipesequals a sum of a thickness of TIM1, a thickness of the lid, a thicknessof TIM2, and a height of the heat sink. Other aspects include thevertical heat pipes including copper (Cu). Additional aspects include adiameter of each vertical heat pipe ranging from 1 millimeter (mm) to awidth of the IC chip with which it is in thermal contact. Furtheraspects include the vertical heat pipes having conductivity in only onedirection.

A further aspect of the present disclosure is a device including: pluralIC chips attached to an upper surface of a substrate; a lid over the ICchips; and a slit through the lid at a boundary between adjacent ICchips.

Aspects of the device include the IC chips including: a logic chip; andat least one memory stack adjacent the logic chip. Other aspects includethe slit formed at a boundary between the logic chip and a memory stack.Further aspects include a slit formed between the logic chip and eachmemory stack. Another aspect includes a heat sink over the lid; and atleast one vertical heat pipe through the heat sink and the lid, down tothe IC chips, wherein each vertical heat pipe is in direct thermalcontact with an IC chip and the heat sink. Additional aspect includes aTIM1 between the lid and the IC chips; and a TIM2 between the heat sinkand the lid, wherein a length of the vertical heat pipes equals a sum ofa thickness of TIM1, a thickness of the lid, a thickness of TIM2, and aheight of the heat sink. Further aspects include the vertical heat pipesincluding Cu. Another aspect includes a diameter of each vertical heatpipe ranging from 1 mm to a width of the IC chip with which it is inthermal contact. Additional aspect includes the vertical heat pipeshaving conductivity in only one direction.

Another aspect of the present disclosure is a method including:attaching IC chips, including a logic chip and at least one memory stackadjacent the logic chip, to an upper surface of a substrate; thermallyconnecting a lid to an upper surface of the IC chips by a TIM1; forminga slit through the lid by punch and die at a boundary between the logicchip and each memory stack; thermally connecting a heat sink to the lidby a TIM2; forming at least one co-axial hole in the lid and the heatsink; and inserting a vertical heat pipe through each hole for directthermal contact with an IC chip and the heat sink, wherein a length ofthe vertical heat pipes equals a sum of a thickness of TIM1, a thicknessof the lid, a thickness of TIM2, and a height of the heat sink, adiameter of each vertical heat pipe ranges from 1 mm to a width of theIC chip with which it is in thermal contact, and the vertical heat pipeshave conductivity in only one direction.

Additional aspects and technical effects of the present disclosure willbecome readily apparent to those skilled in the art from the followingdetailed description wherein embodiments of the present disclosure aredescribed simply by way of illustration of the best mode contemplated tocarry out the present disclosure. As will be realized, the presentdisclosure is capable of other and different embodiments, and itsseveral details are capable of modifications in various obviousrespects, all without departing from the present disclosure.Accordingly, the drawings and description are to be regarded asillustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is illustrated by way of example, and not by wayof limitation, in the figures of the accompanying drawing and in whichlike reference numerals refer to similar elements and in which:

FIG. 1 schematically illustrates heat flow in a semiconductor packagewith adjacent IC chips;

FIG. 2 schematically illustrates a semiconductor package with a slit ata boundary between adjacent IC chips, in accordance with an exemplaryembodiment;

FIG. 3 schematically illustrates a semiconductor package with both aslit at a boundary between adjacent IC chips and a vertical heat pipe indirect thermal contact with an IC chip and a heat sink, in accordancewith an exemplary embodiment; and

FIG. 4 schematically illustrates a top down view of a 2.5D package ofFIG. 3, in accordance with an exemplary embodiment.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of exemplary embodiments. It should be apparent, however,that exemplary embodiments may be practiced without these specificdetails or with an equivalent arrangement. In other instances,well-known structures and devices are shown in block diagram form inorder to avoid unnecessarily obscuring exemplary embodiments. Inaddition, unless otherwise indicated, all numbers expressing quantities,ratios, and numerical properties of ingredients, reaction conditions,and so forth used in the specification and claims are to be understoodas being modified in all instances by the term “about.”

The present disclosure addresses and solves the current problem ofthermal interaction between IC chips attendant upon forming a 2.5Dsemiconductor package with memory stacks close to a logic chip. Inaccordance with embodiments of the present disclosure, thermalinteraction between IC chips can be avoided by forming a slit in themodule lid at IC chip boundaries to stop heat flow from one chip toanother through the lid. Correspondingly, heat flow from one IC chip toanother through a heat sink base can be avoided by forming at least onevertical heat pipe that is inserted through co-axial holes in the heatsink and the lid for direct thermal contact with an IC chip.

Methodology in accordance with embodiments of the present disclosureincludes attaching plural IC chips to an upper surface of a substrateand forming a lid over the IC chips. A slit is formed through the lid ata boundary between adjacent IC chips.

Still other aspects, features, and technical effects will be readilyapparent to those skilled in this art from the following detaileddescription, wherein preferred embodiments are shown and described,simply by way of illustration of the best mode contemplated. Thedisclosure is capable of other and different embodiments, and itsseveral details are capable of modifications in various obviousrespects. Accordingly, the drawings and description are to be regardedas illustrative in nature, and not as restrictive.

FIG. 2 schematically illustrates a semiconductor package with a slit ata boundary between adjacent IC chips, in accordance with an exemplaryembodiment. Similar to the conventional semiconductor package of FIG. 1,FIG. 2 includes a substrate 201 with an upper surface and a lowersurface. Solder balls 203 are metallurgically bonded to solder ballreceiving areas in the lower surface of the substrate 201. A logic chip205 and a memory stack 207 are attached to the upper surface of thesubstrate 201 by C4 balls 209 via an interposer 208. The logic chip 205and the memory stack 207 are mounted on the interposer 208 withmicro-bumps 206. A lid 211 is formed over the logic chip 205 and thememory stack 207. The lid 211 is thermally connected to the logic chip205 and the memory stack 207 by TIM1 213. The TIM1 213 is separated atthe boundary right under the slit to isolate the thermal path. The lid211 also includes lid feet in mechanical contact with a perimeter of theupper surface of the substrate by an adhesive 215. FIG. 2 differs fromFIG. 1 in that a slit 221 is formed through the lid 211 at a boundarybetween the logic chip 205 and the memory stack 207, for example bypunch and die. The punch and die is either integrated in the lid 211fabrication tooling or in a separate tooling. Although only one memorystack is illustrated in FIG. 2 for illustrative convenience, a secondmemory stack (e.g., a hybrid memory cube (HMC) or a high bandwidthmemory (HBM)) could be present on the other side of the custom logic die(e.g., an application-specific integrated circuit (ASIC)). A similarslit in the lid may be formed between the logic chip and any additionalmemory stack. The width of the slit 221 is at least as large as thephysical space separation between the IC chips such that there is nodirect thermal conduction at the slit location. The length of the slit221 needs to be at least the length of the larger IC chip on the eitherside. As illustrated by arrows 223, the slit 221 prevents heat flow fromthe logic chip 205 to the memory stack 207 and vice-versa through thelid 211. In such manner, the slit 221 avoids thermal interaction betweenthe logic chip 205 and the memory stack 207. In addition, a heat sink217 is formed over the lid 211, and is thermally connected to the lid211 by TIM2 219.

FIG. 3 schematically illustrates a semiconductor package with both aslit at a boundary between adjacent IC chips and a vertical heat pipe indirect thermal contact with an IC chip and a heat sink, in accordancewith an exemplary embodiment. FIG. 3 includes the same elements as inFIG. 2. Specifically, solder balls 303 are metallurgically bonded to thesolder balls receiving areas in the lower surface of substrate 301. Alogic chip 305 and a memory stack 307 are attached to the upper surfaceof the substrate 301 by C4 balls 309 via an interposer 308. The logicchip 305 and the memory stack 307 are mounted on the interposer 308 withmicro-bumps 306. A lid 311 is formed over the logic chip 305 and thememory stack 307 and is thermally connected by TIM1 313. The lid 311also includes lid feet in mechanical contact with a perimeter of theupper surface of the substrate 301 by an adhesive 315. A slit 321 isformed through the lid at a boundary between the logic chip 305 and thememory stack 307, e.g., by punch and die. The punch and die is eitherintegrated in the lid 311 fabrication tooling or in a separate tooling.A heat sink 317 is formed over the lid 311, and is thermally connectedto the lid 311 by TIM2 319. The difference between FIG. 3 and FIG. 2 isthat co-axial holes are formed through the lid 311 and the heat sink317. Then, prefabricated vertical heat pipes 323 are inserted throughthe co-axial holes for direct thermal contact between the heat sink 317and both the logic chip 305 and the memory stack 307. The vertical heatpipes 323 prevent heat flow from the logic chip 305 to the memory stack307 and vice-versa through the heat sink base. The vertical heat pipes323 are formed of Cu or any other metal. The length of the vertical heatpipes 323 equals a sum of the thickness of TIM1, the thickness of thelid, the thickness of TIM2, and the height of the heat sink. Thediameter of each vertical heat pipe 323 ranges from 1 mm to a width ofthe IC chip with which it is in thermal contact. The vertical heat pipes323 have conductivity in only one direction. As shown by arrows 325,heat flows from the logic chip away from the memory stack.

FIG. 4 schematically illustrates a top down view of the 2.5D package ofFIG. 3, in accordance with an exemplary embodiment. In FIG. 4, thenumber of the vertical heat pipes 407 shown thermally connected to alogic chip 403 is higher than the number of the vertical heat pipes 407shown thermally connected to a memory stack 405. However, the number ofthe vertical heat pipes 407 on each of the logic chip 403 and the memorystack 405 is based on the diameter of the vertical heat pipes, the sizeof the IC chips and the spacing rules for hole fabrication technology.The thermal conductivity of the vertical heat pipes 407 is 10,000 timeshigher than Cu. In addition, the vertical heat pipes 407 haveconductivity in only one direction; therefore the end of the verticalheat pipes 407 at the logic chip 403 and the memory stack 405 have ahigher temperature, and the other end is at a lower temperature.Further, the inherent very high thermal conductivity of the verticalheat pipes 407 allows effective heat dissipation. Accordingly, the heatfrom the logic chip 403 and the memory stack 405 flows to the top of theheat sink quicker and is dissipated speedily as the temperature deltabetween the heat sink top and ambient air is sufficiently large. Withthe slit and vertical heat pipes in direct thermal contact with both theIC chips and the heat sink, the thermal interaction between IC chips isreduced. A carefully designed vertical heat pipe arrangement can reducethe thermal solution size by almost 25%.

The embodiments of the present disclosure can achieve several technicaleffects, such as, reduced thermal interaction between IC chips, smallerand lighter thermal solution size, faster heat flow from IC chips to thetop of heat sink, faster heat dissipation, etc. Devices formed inaccordance with embodiments of the present disclosure enjoy utility invarious industrial applications, e.g., microprocessors, smart phones,mobile phones, cellular handsets, set-top boxes, DVD recorders andplayers, automotive navigation, printers and peripherals, networking andtelecom equipment, gaming systems, and digital cameras. The presentdisclosure therefore enjoys industrial applicability in any of varioustypes of highly integrated semiconductor devices, particularly for the14 nm technology node and beyond.

In the preceding description, the present disclosure is described withreference to specifically exemplary embodiments thereof. It will,however, be evident that various modifications and changes may be madethereto without departing from the broader spirit and scope of thepresent disclosure, as set forth in the claims. The specification anddrawings are, accordingly, to be regarded as illustrative and not asrestrictive. It is understood that the present disclosure is capable ofusing various other combinations and embodiments and is capable of anychanges or modifications within the scope of the inventive concept asexpressed herein.

What is claimed is:
 1. A device comprising: plural integrated circuit(IC) chips attached to an upper surface of a substrate; a lid over theIC chips; and a slit through the lid at a boundary between adjacent ICchips.
 2. The device according to claim 1, wherein the IC chipscomprise: a logic chip; and at least one memory stack adjacent the logicchip.
 3. The device according to claim 2, wherein the slit is formed ata boundary between the logic chip and a memory stack.
 4. The deviceaccording to claim 2, wherein a slit is formed between the logic chipand each memory stack.
 5. The device according to claim 1, furthercomprising a heat sink over the lid.
 6. The device according to claim 5,further comprising at least one vertical heat pipe through the heat sinkand the lid, down to the IC chips.
 7. The device according to claim 6,wherein each vertical heat pipe is in direct thermal contact with an ICchip and the heat sink.
 8. The device according to claim 7, furthercomprising a first thermal interface material (TIM1) between the lid andthe IC chips.
 9. The device according to claim 8, further comprising asecond thermal interface material (TIM2) between the heat sink and thelid.
 10. The device according to claim 9, wherein a length of thevertical heat pipes equals a sum of a thickness of TIM1, a thickness ofthe lid, a thickness of TIM2, and a height of the heat sink.
 11. Thedevice according to claim 7, wherein the vertical heat pipes comprisecopper (Cu).
 12. The device according to claim 7, wherein a diameter ofeach vertical heat pipe ranges from 1 millimeter (mm) to a width of theIC chip with which it is in thermal contact.
 13. The device according toclaim 7, wherein the vertical heat pipes have conductivity in only onedirection.
 14. A device comprising: plural integrated circuit (IC) chipsattached to an upper surface of a substrate, wherein the IC chipscomprise a logic chip and at least one memory stack adjacent the logicchip; a lid over the IC chips; a slit through the lid at a boundarybetween the logic chip and each memory stack; and a heat sink over thelid.
 15. The device according to claim 14, further comprising at leastone vertical heat pipe through the heat sink and the lid, down to the ICchips.
 16. The device according to claim 15, wherein each vertical heatpipe is in direct thermal contact with an IC chip and the heat sink. 17.The device according to claim 16, further comprising a first thermalinterface material (TIM1) between the lid and the IC chips.
 18. Thedevice according to claim 17, further comprising a second thermalinterface material (TIM2) between the heat sink and the lid.
 19. Thedevice according to claim 18, wherein a length of the vertical heatpipes equals a sum of a thickness of TIM1, a thickness of the lid, athickness of TIM2, and a height of the heat sink.
 20. The deviceaccording to claim 15, wherein each vertical heat pipe comprise copper(Cu).